Silicon Labs /BGM220SC22HNA /RAC_S /CLKMULTEN0

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Interpret as CLKMULTEN0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (bw_1lsb)CLKMULTBWCAL 0 (enable)CLKMULTDISICO 0 (disable)CLKMULTENBBDET 0 (disable)CLKMULTENBBXLDET 0 (disable)CLKMULTENBBXMDET 0 (disable)CLKMULTENCFDET 0 (disable)CLKMULTENDITHER 0 (disable)CLKMULTENDRVADC 0 (disable)CLKMULTENDRVN 0 (disable)CLKMULTENDRVP 0 (disable)CLKMULTENDRVRX2P4G 0 (disable)CLKMULTENFBDIV 0 (disable)CLKMULTENREFDIV 0 (disable)CLKMULTENREG1 0 (disable)CLKMULTENREG2 0 (disable)CLKMULTENREG3 0 (disable)CLKMULTENROTDET 0 (disable)CLKMULTENBYPASS40MHZ 0 (pedes_14uA)CLKMULTFREQCAL 0 (I_80uA)CLKMULTREG2ADJI 0 (v1p28)CLKMULTREG1ADJV 0 (v1p03)CLKMULTREG2ADJV 0 (v1p03)CLKMULTREG3ADJV

CLKMULTENREG3=disable, CLKMULTREG3ADJV=v1p03, CLKMULTENDRVADC=disable, CLKMULTREG1ADJV=v1p28, CLKMULTENREFDIV=disable, CLKMULTENBBDET=disable, CLKMULTENREG2=disable, CLKMULTREG2ADJI=I_80uA, CLKMULTFREQCAL=pedes_14uA, CLKMULTENBYPASS40MHZ=disable, CLKMULTENDRVN=disable, CLKMULTENDITHER=disable, CLKMULTENBBXLDET=disable, CLKMULTENFBDIV=disable, CLKMULTENBBXMDET=disable, CLKMULTDISICO=enable, CLKMULTBWCAL=bw_1lsb, CLKMULTENREG1=disable, CLKMULTENDRVP=disable, CLKMULTENROTDET=disable, CLKMULTENDRVRX2P4G=disable, CLKMULTREG2ADJV=v1p03, CLKMULTENCFDET=disable

Fields

CLKMULTBWCAL

CLKMULTBWCAL

0 (bw_1lsb): undefined

1 (bw_2lsb): undefined

2 (bw_3lsb): undefined

3 (bw_4lsb): undefined

CLKMULTDISICO

CLKMULTDISICO

0 (enable): undefined

1 (disable): undefined

CLKMULTENBBDET

CLKMULTENBBDET

0 (disable): undefined

1 (enable): undefined

CLKMULTENBBXLDET

CLKMULTENBBXLDET

0 (disable): undefined

1 (enable): undefined

CLKMULTENBBXMDET

CLKMULTENBBXMDET

0 (disable): undefined

1 (enable): undefined

CLKMULTENCFDET

CLKMULTENCFDET

0 (disable): undefined

1 (enable): undefined

CLKMULTENDITHER

CLKMULTENDITHER

0 (disable): undefined

1 (enable): undefined

CLKMULTENDRVADC

CLKMULTENDRVADC

0 (disable): undefined

1 (enable): undefined

CLKMULTENDRVN

CLKMULTENDRVN

0 (disable): undefined

1 (enable): undefined

CLKMULTENDRVP

CLKMULTENDRVP

0 (disable): undefined

1 (enable): undefined

CLKMULTENDRVRX2P4G

CLKMULTENDRVRX2P4G

0 (disable): undefined

1 (enable): undefined

CLKMULTENFBDIV

CLKMULTENFBDIV

0 (disable): undefined

1 (enable): undefined

CLKMULTENREFDIV

CLKMULTENREFDIV

0 (disable): undefined

1 (enable): undefined

CLKMULTENREG1

CLKMULTENREG1

0 (disable): undefined

1 (enable): undefined

CLKMULTENREG2

CLKMULTENREG2

0 (disable): undefined

1 (enable): undefined

CLKMULTENREG3

CLKMULTENREG3

0 (disable): undefined

1 (enable): undefined

CLKMULTENROTDET

CLKMULTENROTDET

0 (disable): undefined

1 (enable): undefined

CLKMULTENBYPASS40MHZ

CLKMULTENBYPASS40MHZ

0 (disable): undefined

1 (enable): undefined

CLKMULTFREQCAL

CLKMULTFREQCAL

0 (pedes_14uA): undefined

1 (pedes_22uA): undefined

2 (pedes_30uA): undefined

3 (pedes_38uA): undefined

CLKMULTREG2ADJI

CLKMULTREG2ADJI

0 (I_80uA): undefined

1 (I_100uA): undefined

2 (I_120uA): undefined

3 (I_140uA): undefined

CLKMULTREG1ADJV

CLKMULTREG1ADJV

0 (v1p28): undefined

1 (v1p32): undefined

2 (v1p33): undefined

3 (v1p38): undefined

CLKMULTREG2ADJV

CLKMULTREG2ADJV

0 (v1p03): undefined

1 (v1p09): undefined

2 (v1p10): undefined

3 (v1p16): undefined

CLKMULTREG3ADJV

CLKMULTREG3ADJV

0 (v1p03): undefined

1 (v1p06): undefined

2 (v1p07): undefined

3 (v1p09): undefined

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